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never stop thinking. hys72d16000gr-[7/8]-a hys72d32001gr-[7/8]-a registered ddr sdram-modules ddr sdram data sheet, rev. 1.04, jan. 2004 memory products
edition 2004-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys72d16000gr-[7/8]-a hys72d32001gr-[7/8]-a registered ddr sdram-modules ddr sdram data sheet, rev. 1.04, jan. 2004 memory products
template: mp_a4_v2.2_2003-10-07.fm hys72d16000gr-[7/8]-a hys72d32001gr-[7/8]-a revision history: rev. 1.04 2004-01 previous version: rev. 1.03 2003-10 page subjects (major changes since last revision) rev. 1.04 16 editorial and table-layout changes we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules table of contents page data sheet 5 rev. 1.04, 2004-01 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 current specification and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules overview data sheet 6 rev. 1.04, 2004-01 10282003-roli-0gq8 1overview 1.1 features ? 184-pin registered 8 byte dual-in-line ddr sdram module for pc and server main memory applications one bank 16m 72 and 32m 72 organization jedec standard double data rate synchrono us drams (ddr sdram) with a single +2.5 v ( 0.2 v) power supply built with 128 mbit ddr sdrams in 66-lead tsopii package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible re-drive for all input signals using register and pll devices. serial presence detect with e 2 prom jedec standard mo-206 form factor: 133.35 mm (nom.) 43.18 mm (nom.) 4.00 mm (max.) (6,80 mm max. with stacked components) jedec standard reference layout: raw cards a, b and c gold plated contacts table 1 performance -8/-7 1.2 description the hys 72d 0 0gr are industry standard 184-pin 8 byte dual in-line memory modules (dimms) organized as 16m 72 (128 mb) and 32m 72 (256 mb). the memory array is desi gned with double data rate synchronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. part number speed code ?7 ? 8unit speed grade component ddr266a ddr200 ? module pc2100-2033 pc1600-2022 ? max. clock frequency @cl2.5 f ck2.5 143 125 mhz @cl2 f ck2 133 100 mhz
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules overview data sheet 7 rev. 1.04, 2004-01 10282003-roli-0gq8 note: all part numbers end with a pl ace code (not shown), designating th e silicon-die revision. reference information available on request. example: hys72d16000gr-8-a, indicating rev. a die are used for sdram components the compliance code is printed on the module labels and describes the speed sort for example ?pc2100r?, the latencies (for example ?20330? means cas latency = 2, t rcd latency = 3 and t rp latency = 3 ) and the raw card used for this module. table 2 ordering information type compliance code d escription sdram technology pc2100 (cl=2) hys72d16000gr-7-a pc2100r-20330-a1 one bank 128 mb reg. dimm 128 mbit ( 8) hys72d32001gr-7-a pc2100r-20330-b1 one bank 256 mb reg. dimm 128 mbit ( 4) pc1600 (cl=2) hys72d16000gr-8-a pc1600r-20220-a1 one bank 128 mb reg. dimm 128 mbit ( 8) HYS72D32001GR-8-A pc1600r-20220-b1 one bank 256 mb reg. dimm 128 mbit ( 4)
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules pin configuration data sheet 8 rev. 1.04, 2004-01 10282003-roli-0gq8 2 pin configuration *) for detailed description of the power up and power managem ent on ddr registered dimms see the application note at the end of this datasheet table 3 pin definitions and functions symbol type function a0 ? a11 input address inputs ba0, ba1 input rank selects dq0 ? dq63 input/output data input/output cb0 ? cb7 input/output check bits ( 72 organization only) ras input row address strobe cas input column address strobe we input read/write input cke0, cke1 input clock enable dqs0 ? dqs8 input/output sdram low data strobes ck0, ck0 input differential clock input dm0 ? dm8 input sdram low data mask dqs9 ? dqs17 input/output high data strobes cs0 , cs1 input chip selects v dd supply power (+2.5 v) v ss supply ground v ddq supply i/o driver power supply v ddid output v dd indentification flag v ddspd supply eeprom power supply v ref supply i/o reference supply scl input serial bus clock sda output serial bus data line sa0 ? sa2 input slave address select nc input no connect du input don?t use reset input reset pin (forces register inputs low) *) table 4 address format density organization memory ranks sdrams # of sdrams # of row/rank/ columns bits refresh period interval 128 mb 16m 72 1 16m 8 9 12/2/10 4k 64 ms 15.6 s 256 mb 32m 72 1 32m 4 18 12/2/11 4k 64 ms 15.6 s
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules pin configuration data sheet 9 rev. 1.04, 2004-01 10282003-roli-0gq8 table 5 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ref 48 a0 94 dq4 141 a10 2 dq0 49 cb2 95 dq5 142 cb6 3 v ss 50 v ss 96 v ddq 143 v ddq 4 dq1 51 cb3 97 dm0/dqs9 144 cb7 5 dqs0 52 ba1 98 dq6 key 6dq2 key 99 dq7 145 v ss 7 v dd 53 dq32 100 v ss 146 dq36 8dq3 54 v ddq 101 nc 147 dq37 9 nc 55 dq33 102 nc 148 v dd 10 reset 56 dqs4 103 nc 149 dm4/dqs13 11 v ss 57 dq34 104 v ddq 150 dq38 12 dq8 58 v ss 105 dq12 151 dq39 13 dq9 59 ba0 106 dq13 152 v ss 14 dqs1 60 dq35 107 dm1/dqs10 153 dq44 15 v ddq 61 dq40 108 v dd 154 ras 16 du 62 v ddq 109 dq14 155 dq45 17 du 63 we 110 dq15 156 v ddq 18 v ss 64 dq41 111 cke1 157 cs0 19 dq10 65 cas 112 v ddq 158 cs1 20 dq11 66 v ss 113 nc 159 dm5/dqs14 21 cke0 67 dqs5 114 dq20 160 v ss 22 v ddq 68 dq42 115 nc/a12 a12 is used for 256 mbit and 512 mbit based modules only 161 dq46 23 dq16 69 dq43 116 v ss 162 dq47 24 dq17 70 v dd 117 dq21 163 nc 25 dqs2 71 nc 118 a11 164 v ddq 26 v ss 72 dq48 119 dm2/dqs11 165 dq52 27 a9 73 dq49 120 v dd 166 dq53 28 dq18 74 v ss 121 dq22 167 nc 29 a7 75 du 122 a8 168 v dd 30 v ddq 76 du 123 dq23 169 dm6/dqs15 31 dq19 77 v ddq 124 v ss 170 dq54 32 a5 78 dqs6 125 a6 171 dq55 33 dq24 79 dq50 126 dq28 172 v ddq 34 v ss 80 dq51 127 dq29 173 nc 35 dq25 81 v ss 128 v ddq 174 dq60 36 dqs3 82 v ddid 129 dm3/dqs12 175 dq61 37 a4 83 dq56 130 a3 176 v ss 38 v dd 84 dq57 131 dq30 177 dm7/dqs16
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules pin configuration data sheet 10 rev. 1.04, 2004-01 10282003-roli-0gq8 39 dq26 85 v dd 132 v ss 178 dq62 40 dq27 86 dqs7 133 dq31 179 dq63 41 a2 87 dq58 134 cb4 180 v ddq 42 v ss 88 dq59 135 cb5 181 sa0 43 a1 89 v ss 136 v ddq 182 sa1 44 cb0 90 nc 137 ck0 183 sa2 45 cb1 91 sda 138 ck0 184 v ddspd 46 v dd 92 scl 139 v ss 185 v ss 47 dqs8 93 v ss 140 dm8/dqs17 ? ? table 5 pin configuration (cont?d) pin# symbol pin# symbol pin# symbol pin# symbol
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules pin configuration data sheet 11 rev. 1.04, 2004-01 10282003-roli-0gq8 figure 1 block diagram one rank 16 mb 72 ddr sdram dimm modules hys72d16000gr-[7/8]-a using 8 organized sdrams on raw card version a pck pck dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm0/dqs9 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4/dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm7/dqs16 rs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 i/o 5 i/o 4 i/o 3 i/o 2 cs dqs8 dm8/dqs17 dqs dqs dqs dqs dqs ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams cs0 rs 0 -> cs : sdrams d0-d8 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d8 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d8 ras rras -> ras : sdrams d0 - d8 cas rcas -> cas : sdrams d0 - d8 cke0 rcke0 -> cke: sdrams d0 - d8 we rwe -> we : sdrams d0 - d8 r e g i s t e r reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss d0 - d8 d0 - d8 v ddq d0 - d8 d0 - d8 vref v ddid strap: see note 4 v ddspd eeprom a0 serial pd a1 a2 sa0 sa1 sa2 scl sda
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules pin configuration data sheet 12 rev. 1.04, 2004-01 10282003-roli-0gq8 figure 2 block diagram one rank 32 mb 72 ddr sdram dimm modules hys72d32001gr-[7/8]-a using 4 organized sdrams on raw card version b rs 0a dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cb0 cb1 cb2 cb3 dqs d8 cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs vss dqs1 dqs3 dqs8 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 dm8/dqs17 rs 0b ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a11,a12 ra0-ra11,ra12 -> a0-a11,a12: sdrams d0 - d17 ras rras -> ras : sdrams d0 - d17 cs0 cas rcas -> cas : sdrams d0 - d17 cke0 rcke0a -> cke: sdrams d0 - d8 we rwe -> we : sdrams d0 - d17 r e g i s t e r rckeb -> cke: sdrams d9 - d17 pck pck reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss v ddq vref v ddid strap: see note 4 v ddspd eeprom d0 - d17 d0 - d17 d0 - d17 rs 0 -> cs : sdrams d0-d17
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 13 rev. 1.04, 2004-01 10282003-roli-0gq8 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occu r if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 6 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma?
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 14 rev. 1.04, 2004-01 10282003-roli-0gq8 table 7 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v output supply voltage v ddq 2.3 2.5 2.7 v 2) 2) under all conditions, v ddq must be less than or equal to v dd . supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 3) 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 4) 4) v tt is not applied dire ctly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 7) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 7) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 7) input different ial voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 7)5) 5) v id is the magnitude of the difference between th e input level on ck and the input level on ck . vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 6) 6) the ratio of the pull-up current to the pull-down current is specified for the sa me temperature and volt age, over the entire temperature and voltage range, for device drain to source volt age from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 7)8) 7) inputs are not recognized as valid until v ref stabilizes. 8) values are shown per component output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 7) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v 7) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 7)
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 15 rev. 1.04, 2004-01 10282003-roli-0gq8 table 8 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs chan ging once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; powe r-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 16 rev. 1.04, 2004-01 10282003-roli-0gq8 table 9 i dd specification and conditions part number & organization hys72d16000gr-7-a hys72d32001gr-7-a hys72d16000gr-8-a hys72d16000gr-8-a unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition fo r maximum values: v dd =2.7v, t a =10c 128mb 256mb 128mb 256mb x72 x72 x72 x72 1 rank 1 rank 1 rank 1 rank ?7 ?7 ?8 ?8 symbol max. max. max. max. i dd0 810 1620 765 1530 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 990 1980 900 1800 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 45 90 40.5 81 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 405 810 315 630 ma 5) i dd2q 405 810 315 630 ma 5) i dd3p 135 270 135 270 ma 5) i dd3n 405 810 315 630 ma 5) i dd4r 990 1980 810 1620 ma 3)4) i dd4w 990 1980 855 1710 ma 3) i dd5 1710 3420 1620 3240 ma 3) i dd6 22.5 45 22.5 45 ma 5) i dd7 2520 5040 2430 4860 ma 3)4)
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 17 rev. 1.04, 2004-01 10282003-roli-0gq8 3.2 current specifi cation and conditions 3.3 ac characteristics table 10 ac timing - absolute specifications ?8/?7 parameter symbol ?8 ?7 unit note/ test condition 1) ddr200 ddr266a min. max. min. max. dq output access time from ck/ck t ac ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck2.5 8 12 7 12 ns cl = 2.5 2)3)4)5) t ck2 10 12 7.5 12 ns cl = 2.0 2)3)4)5) t ck1.5 10 12 ? ? ns cl = 1.5 2)3)4)5) dq and dm input hold time t dh 0.6 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.6 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.5 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 2.0 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.8 +0.8 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.6 ? +0.5 ns 2)3)4)5) data hold skew factor t qhs ? 1.0 ? 0.75 ns 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2? 2 ? t ck 2)3)4)5) write preamble setup time t wpres 0? 0 ? ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5)
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 18 rev. 1.04, 2004-01 10282003-roli-0gq8 address and control input setup time t is 1.1 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 1.1 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.1 ? 1.0 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck cl > 1.5 2)3)4)5) t rpre1.5 0.9 1.1 na t ck cl = 1.5 2)3)4)5)11) read preamble setup time t rpres 1.5 ? na ns 2)3)4)5)12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 50 120e+3 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 70 ? 65 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 80 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? 20 ? ns 2)3)4)5) precharge command period t rp 20 ? 20 ? ns 2)3)4)5) active to autoprecharge delay t rap 20 ? 20 ? ns 2)3)4)5) active bank a to active bank b command t rrd 15 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)13) internal write to read command delay t wtr 1? 1 ? t ck cl > 1.5 2)3)4)5) t wtr1.5 2? ? ? t ck cl = 1.5 2)3)4)5) exit self-refresh to non-read command t xsnr 80 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)14) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate 1 v/ns for ddr266, and = 1 v/ns for ddr200 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as me asured at the timing reference point indica ted in ac characteristics (note 3) is v tt . 6) these parameters guarantee devi ce timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) the specific requirement is t hat dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew ra te specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . table 10 ac timing - absolute specifications ?8/?7 parameter symbol ?8 ?7 unit note/ test condition 1) ddr200 ddr266a min. max. min. max.
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules electrical characteristics data sheet 19 rev. 1.04, 2004-01 10282003-roli-0gq8 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnar ound) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 11) cas latency 1.5 operation is supported on ddr200 devices only 12) t rpres is defined for cl = 1.5 operation only 13) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 14) a maximum of eight autorefresh commands can be posted to any given ddr sdram device.
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules spd contents data sheet 20 rev. 1.04, 2004-01 10282003-roli-0gq8 4spdcontents table 11 spd codes byte# description 128mb x72 1rank ?7 128mb x72 1rank ?8 256mb x72 1rank ?7 256mb x72 1rank ?8 hex. hex. hex. hex. 0 number of spd bytes 128 80 80 80 80 1 total bytes in serial pd 256 08 08 08 08 2 memory type ddr-sdram 07 07 07 07 3 number of row addresses 12 0c 0c 0c 0c 4 number of column addresses 10/11 0a 0a 0b 0b 5 number of dimm banks 1 01 01 01 01 6 module data width 72 48 48 48 48 7 module data width (cont?d) 0 00 00 00 00 8 module interface levels sstl_2.5 04 04 04 04 9 sdram cycle time at cl = 2.5 7 ns/8 ns 70 80 70 80 10 access time from clock at cl = 2.5 0.75 ns/0.8 ns 75 80 75 80 11 dimm config ecc 02020202 12 refresh rate/type self-refresh 15.6 ms 80 80 80 80 13 sdram width, primary 8/ 4 08080404 14 error checking sdram data witdh na 08 08 04 04 15 minimum clock delay for back- to-back random column address t ccd =1 clk 01010101 16 burst length supported 2, 4 & 8 0e 0e 0e 0e 17 number of sdram banks 4 04 04 04 04 18 supported cas latencies cas latency = 2 & 2.5 0c 0c 0c 0c 19 cs latencies cs latency = 0 01 01 01 01 20 we latencies write latency = 1 02 02 02 02 21 sdram dimm module attributes registered 26 26 26 26 22 sdram device attributes: general concurrent auto precharge c0 c0 c0 c0 23 min. clock cycle time at cas latency = 2 7.5 ns/10 ns 75 a0 75 a0 24 access time from clock for cl = 2 0.75 ns/0.8 ns 75 80 75 80 25 minimum clock cycle time for cl = 1.5 not supported 00 00 00 00 26 access time from clock at cl = 1.5 not supported 00 00 00 00
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules spd contents data sheet 21 rev. 1.04, 2004-01 10282003-roli-0gq8 27 minimum row precharge time 20 ns 50 50 50 50 28 minimum row act. to row act. delay t rrd 15 ns 3c 3c 3c 3c 29 minimum ras to cas delay t rcd 20 ns 50 50 50 50 30 minimum ras pulse width t ras 45ns/50ns 2d32 2d32 31 module bank density (per bank) 128 mbyte/256 mbyte 20 20 40 40 32 addr. and command setup time 0.9 ns/1.1 ns 90 b0 90 b0 33 addr. and command hold time 0.9 ns/1.1 ns 90 b0 90 b0 34 data input setup time 0.5 ns/0.6 ns 50 60 50 60 35 data input hold time 0.5 ns/0.6 ns 50 60 50 60 36 to 40 superset information ? 00 00 00 00 41 minimum core cycle time t rc 65ns/70ns 41464146 42 min. auto refresh cmd cycle time t frc 75ns/80ns 4b50 4b50 43 maximum clock cycle time t ck 12 ns 0c 0c 0c 0c 44 max. dqs-dq skew tdqsq 0.5 ns/0.6 ns 32 3c 32 3c 45 x-factor tqhs 0.75 ns/1.0 ns 75 a0 75 a0 46 to 61 superset information ? 00 00 00 00 62 spd revision revision 0.0 00 00 00 00 63 checksum for bytes 0 - 62 ? a7 9c c0 b5 64 manufactures jedec id codes ? c1 c1 c1 c1 65 to 71 manufactures ? infineon infineon infineon infineon 72 module assembly location? ???? 73 to 90module part number ? ???? 91 to 92module revision code ? ???? 93 to 94module manufacturing date? ???? 95 to 98module serial number ? ???? 99 to 127? ? ???? 128 to 255open for customer use ? ???? table 11 spd codes (cont?d) byte# description 128mb x72 1rank ?7 128mb x72 1rank ?8 256mb x72 1rank ?7 256mb x72 1rank ?8 hex. hex. hex. hex.
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules package outlines data sheet 22 rev. 1.04, 2004-01 10282003-roli-0gq8 5 package outlines figure 3 package outlines raw card a module package ddr registered dimm modules raw card a, 128 mb module (one physical bank, 9 components) l-dim-184-10, raw card a, one bank 144 145 184 17.80 3 10.0 3 detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 43.18 pin 1 + 0.13 - + 0.15 - 6.62 49.53 4.0 1.27 4.0 max. + 0.1 - pin 93 2.5d front view backside view detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r pll register register
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules package outlines data sheet 23 rev. 1.04, 2004-01 10282003-roli-0gq8 figure 4 package outlines raw card b module package ddr registered dimm modules raw card b, 256 mb module (one physical bank, 18 components) l-dim-184-8, raw card b 144 145 184 17.80 3 10.0 3 detail of contacts a 2.5 1 1.27 0.20 + 0.05 - + 0.20 - + 0.15 - 133.35 2.3 typ. 53 52 64.77 92 2.3 typ. 43.43 pin 1 + 0.13 - + 0.15 - 6.62 49.53 4.0 1.27 4.0 max. + 0.1 - pin 93 2.5d front view backside view detail of contacts b 3.8 typ. 2.175 6.35 1.8 0.9r pll register register
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules application note data sheet 24 rev. 1.04, 2004-01 10282003-roli-0gq8 6 application note power up and power management on ddr registered dimms (according to jedec ballot jc-42.5 item 1173) 184-pin double data rate (ddr) registered dimms include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. one feature is externally controlled via a system- generated reset signal; the second is based on module detection of the input clocks. these enhancements permit the modules to power up with sdram outputs in a hi gh-z state (eliminating risk of high current dissipations and/or dotted i/os), and result in the powering-down of module support devices (registers and phase-locked loop) when the memory is in self-refresh mode. the new reset pin controls power dissipation on the module?s registers and ensures that cke and other sdram inputs are maintained at a va lid ?low? level during power-up and self refresh. when reset is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register po wer consumption. the reset pin, located on dimm tab #10, is driven from the system as an asynchronous signal according to the attached details . using this function also permits the system and dimm clocks to be stopped during memory self refresh operation, while ensuring that the sdrams stay in self refresh mode. as described in the table above, a low on the reset input ensures that the clock enable (cke) signal(s) are maintained low at the sdram pins (cke being one of the 'q' signals at the register output). holding cke low maintains a high impedance state on the sdram dq, dqs and dm outputs ? wher e they will remain until activated by a valid ?read? cycle. cke low also main tains sdrams in self refr esh mode when applicable. the ddr pll devices automatically detect clock activity above 20 mhz. when an input clock frequency of 20 mhz or greater is detected, the pll begins operation and initiates clock frequency lock (the minimum operating frequency at which all spec ifications will be met is 95 mhz). if t he clock input frequenc y drops below 20 mhz (actual detect frequency will vary by ve ndor), the pll vco (voltage controlled oscillator) is stopped, outputs are made high-z, and the differential inputs are powered down ? resulting in a total pll current consumption of less than 1 ma. use of this low power pll function makes the use of the pll reset (or g pin) unnecessary, and it is tied inactive on the dimm. this application note describes the requ ired and optional system sequences associated with the ddr registered dimm 'reset ' function. it is important to note that all references to cke refer to both cke0 and cke1 for a 2-bank dimm. because reset applies to all dimm regist er devices, it is therefore not possible to un iquely control cke to one physical di mm bank through the use of the reset pin. power-up sequence with reset ? required 1. the system sets reset at a valid low level. this is the preferred default state during power-up. this input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that cke is at a stable low-level at the ddr sdrams. table 12 reset truth table register inputs register outputs reset ck ck data in (d) data out (q) h rising falling h h h rising falling l l h l or h l or h x qo h high z high z x illegal input conditions l x or hi-z x or hi-z x or hi-z l x: don?t care, hi-z: hig h impedance, qo: data latched at the previous of ck rising and ck falling
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules application note data sheet 25 rev. 1.04, 2004-01 10282003-roli-0gq8 2. the power supplies should be init ialized according to the jedec-appr oved initialization sequence for ddr sdrams. 3. stabilization of clocks to the sdram the system must drive clocks to the application frequency (pll operation is not assured until the input clock reaches 20 mhz). stability of clocks at the sdrams will be affected by all applic able system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, the required pll stabilization time (assuming power to the dimm is stable) is 100 microseconds. when a stable clock is present at the sdram input (d riven from the pll), the ddr sdram requires 200 sec prior to sdram operation. 4. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the firs t command defined by the jedec initia lization sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receiv e commands. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 5. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time ( t (act) ), from asynchro nous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 7. the system can begin the jedec-defined ddr sdram power-up sequence (according to the jedec- pproved initialization sequence). self refresh entry (reset low, clocks powered off) ? optional self refresh can be used to retain data in ddr sdram dimms even if the rest of the system is powered down and the clocks are off. this mode allows the ddr sdrams on the dimm to retain data without external clocking. self refresh mode is an id eal time to utilize the reset pin, as this can reduce register power consumption (reset low deactivates register ck and ck, data input receivers, and data output drivers). 1. the system applies self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don?t cares? with the exception of cke.the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that cke, and a ll other control and address signals, are a stable low- level at the ddr sdrams. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required. 2. the system turns off clock inputs to the dimm. (optional) a. in order to reduce dimm pll current, the clock inputs to the dimm are turned off, resulting in high-z clock inputs to both the sdrams and the registers. this must be done after the reset deactivate time of the register ( t (inact) ) . the deactivate time defines the time in wh ich the clocks and the control and address signals must maintain valid levels after reset low has been applied and is sp ecified in the register and dimm documentation. b. the system may release dimm addre ss and control inputs to high-z. this can be done after the reset deactivate time of the register. the deactivate time defines the time in which
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules application note data sheet 26 rev. 1.04, 2004-01 10282003-roli-0gq8 the clocks and the control and the address si gnals must maintain va lid levels after reset low has been applied. it is highly recommended that cke continue to remain low during this operation. 3. the dimm is in lowest power self refresh mode. self refresh exit (reset low, clocks powered off) ? optional 1. stabilization of clocks to the sdram. the system must drive clocks to the application frequency (pll operation is not assured until the input clock reaches ~ 20 mhz). stability of clocks at the sdrams w ill be affected by all applic able system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, the required pll stabilizat ion time (assuming powe r to the dimm is stab le) is 100 microseconds. 2. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the jedec self refresh exit sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receiv e commands. since the reset signal is asynchronous, reset timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 2. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time ( t (act) ), from asynchro nous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 5. system can begin the jedec-defined ddr sdram self refresh exit procedure. self refresh entry (reset low, clocks running) ? optional although keeping the clocks running increases power consumption from the on-dimm pll during self refresh, this is an alternate operating mode for these dimms. 1. system enters self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don?t cares ? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that cke is a stable low-level at the ddr sdrams. 3. the system may release dimm addres s and control inputs to high-z. this can be done after the reset deactivate time of the register ( t (inact) ). the deactivate time describes the time in which the clocks and th e control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during the operation. 4. the dimm is in a low power, self refresh mode. self refresh exit (reset low, clocks running) ? optional 1. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the self refresh exit sequence (ideally this would be
hys72d[16000/32001] gr-[7/8]-a registered ddr sdram modules application note data sheet 27 rev. 1.04, 2004-01 10282003-roli-0gq8 a ?nop deselect? command). a second optio n is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. the system switches reset to a logic 'high' level. the sdram is now functional and prepared to receiv e commands. since the reset signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 1. it is also a functional requirement that the registers maintain a low state at the cke outputs in order to guarantee that the ddr sdrams continue to receive a low level on cke. this activation time, from asynchronous switching of reset from low to high, until the registers are stable and ready to accept an input signal, is t (act ) as specified in the register and dimm documentation. 4. the system can begin jedec defined ddr sdram self refresh exit procedure. self refresh entry/exit (reset high, clocks running) ? optional as this sequence does not involve the use of the reset function, the jedec standard sdram specification explains in detail the method for entering and exiting self refresh for this case. self refresh entry (reset high, clocks powered off) ? not permissible in order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on cke, or the clocks are powered off and reset is asserted low according to the sequence defined in this application note . in the case where reset remains high and the clocks are powered off, the pll drives a high-z clock input into the register clock input. without the low level on reset an unknown dimm state will result.
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